FAULT DECTECTION ARCHITECTURE ON PARALLEL GAUSSIAN NORMAL BASIS MULTIPLIER OVER GF(2^N)

摘要

The present invention relates to an error detection method for a finite field parallel multiplier, which comprises the steps of: predicting a first parity bit by using each bit for a first input of the parallel multiplier and each bit for a second input of the parallel multiplier; and comparing each bit value calculated by parallel multiplication of the first input and the second input with the first parity bit to detect an error, thereby ensuring safety against fault injection attacks on the parallel multiplier by using the parity bit.