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New command - and highly efficient microarchitecture in order to make possible an immediate context switch for levels for users - threading

机译:新的命令-高效的微体系结构,以便立即为用户级别切换上下文-线程化

摘要

A processor uses a plurality of banks of an extended register set for storing the context of a plurality of levels for users - threads. A current bank register is a pointer to the bank, which is currently active, ready. A first thread ensures its context (first context) in a first bank of the extended register set, and a second thread ensures its context (second context) in a second bank of the extended register set. If the processor a command for the exchange of contexts between the first thread and the second thread, changes the processor, the pointer of the first bank to the second bank and leads the second thread with the use of the second context, which is stored in the second bank.
机译:处理器使用扩展寄存器组的多个存储体来为用户-线程存储多个级别的上下文。当前存储体寄存器是指向当前处于活动状态的存储体的指针。第一线程在扩展寄存器组的第一存储体中确保其上下文(第一上下文),第二线程在扩展寄存器组的第二存储体中确保其上下文(第二上下文)。如果处理器在第一线程和第二线程之间交换上下文的命令更改了处理器,则第一存储体的指针指向第二存储体,并使用第二上下文引导第二线程,该第二上下文存储在第二银行。

著录项

  • 公开/公告号DE112013003731T5

    专利类型

  • 公开/公告日2015-05-21

    原文格式PDF

  • 申请/专利权人 INTEL CORPORATION;

    申请/专利号DE20131103731T

  • 发明设计人 DORON ORENSTEIN;

    申请日2013-06-24

  • 分类号G06F9/312;G06F9/46;G06F12/00;G06K9/38;

  • 国家 DE

  • 入库时间 2022-08-21 14:55:24

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