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System and method for selecting a derating factor to balance use of components having disparate electrical characteristics
System and method for selecting a derating factor to balance use of components having disparate electrical characteristics
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机译:用于选择降额因数以平衡具有不同电气特性的组件的使用的系统和方法
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摘要
A test system and method for selecting a derating factor to be applied to a ratio of transistors having disparate electrical characteristics in a wafer fabrication process. In one embodiment, the test system includes: (1) structural at-speed automated test equipment (ATE) operable to iterate structural at-speed tests at multiple clock frequencies over integrated circuit (IC) samples fabricated under different process conditions and (2) derating factor selection circuitry coupled to the structural at-speed ATE and configured to employ results of the structural at-speed tests to identify performance deterioration in the samples, the performance deterioration indicating the derating factor to be employed in a subsequent wafer fabrication process.
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