FUNCTIONAL STRUCTURE OF PRE-ADDER f₁(Σ_CD) OF CONDITIONAL 'j' BIT OF PARALLEL-SERIAL MULTIPLIER f_Σ(Σ) IMPLEMENTING PROCEDURE FOR 'DECRYPTION' OF ARGUMENTS OF PARTIAL PRODUCTS WITH STRUCTURES OF ARGUMENTS OF MULTIPLICAND m_jf(2ⁿ) AND MULTIPLIER n_if(2ⁿ) IN POSITION FORMAT OF 'ADDITIONAL CODE' AND FORMATION OF INTERMEDIATE SUM ^1,2Sj^h1f(2ⁿ) IN POSITION FORMAT OF 'ADDITIONAL CODE RU' (RUSSIAN LOGIC VERSIONS)

摘要

FIELD: computer engineering.;SUBSTANCE: group of inventions relates to computer engineering and can be used in designing parallel-serial multiplier with input arguments of terms [m_j]f(2ⁿ) and [n_i]f(2ⁿ) in “complementary code” format. In one version, structure is realised using logic elements AND, OR, NOT, AND-NOT, OR-NOT.;EFFECT: high efficiency of converting input arguments.;2 cl