Processor - model, which is a single large, linear register is used, with fifo - based i / o - ports supporting new interface - signals and interrupt-driven bus - transfers, the dma, bridges and an external i / o - bus eliminate

摘要

A processor or a cpu - architecture, the or the number of technologies that is implemented, which have been proven, in order to obtain a data throughput, the synchronous bitbündeldatenübertragung, to increase. The input - output (e / a) a uniform and is considered as individual first -, - first -, - (fifo -; fifo = first - in - first - out) device. A plurality of memory components, which is for a user stack, the core stack and under refraction implemented procedure call stack. Only an e / a - feeder is necessary for a cpu - model between a plurality of fifo allocates, wherein an implementation on a chip by data - said cache is exchanged, so that conventional method of data transmission using a direct memory access (dma; dma = direct - memory - access) are eliminated, buss expensive - and locking signals only the interrupt signals and the new synchronous signals for a light and streamlined configuration of the system design and leave behind a cpu - model. By means of a support of a refraction driven fifo - based e / a and a synchronous bitbündeldatenübertragung, the cpu simple linear large register sets without a bank switching.