Device for analog-digital conversion in temporally improved sequence and modified type of the known pipelined ADC by parallel arrangement in contrast to the current state of the art temporally serial arranged processes within the individual converter stages.

摘要

Device for analog-digital conversion in temporally improved sequence and modified type of the known pipelined ADCs by parallel arrangement in contrast to the current state of the art temporally serial arranged processes within the individual converter stages, characterized in that 1) A temporally parallel running topology is present after the involves the AD / DA branch as well as the gain and memory / hold link. 2) After 1) a doubling of the sample rate can be achieved. 3) The signal combination from the DA stage n-1 behind the amplifier of n-2 takes place after 2. 4) This can be done in signal merge of 3) in the time clock after storage or, if appropriate, in the same clock storage. 5) in the input-side converter stage a signal routing in an active or passive manner with Vu = 1 takes place after 4. 6) The scheme according to 2 or 3 is applicable at least in comparison to 1 or the prior art.