Checking a correctness of computations of an arithmetic logic unit circuit 10, the arithmetic logic unit circuit 10 providing a computation result as a first number 12. The method comprises providing the computation result increased by a constant 16 by the arithmetic logic unit circuit 10 as a second number 14 and comparing a sum of the first number 12 and the constant 16 to the second number 14 then reporting an error 20 if the comparing operation does not indicate an equal result. Alternatively the first number may be summed with the negated second number 14 and the constant 16 and an error reported if the summing operation does not result to minus 1. The computation result and the computation result being increased by a constant may be calculated in parallel. The method allows the reuse of computed results to check for correctness of computations.
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