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Methods for contact formation for 10 nanometers and beyond with minimal mask counts

机译:最少的掩模数量即可形成10纳米及以上的触点

摘要

A method of making a semiconductor device includes depositing a hard mask on a dielectric layer on a substrate, the dielectric layer being disposed around first, second, and third gates; removing a portion of the hard mask to form an opening that exposes the first, second, and third gates; forming a patterned soft mask on the first, second, and third gates within the opening, a first portion of the patterned soft mask being disposed on the first and second gates, and a second portion of the patterned soft mask being disposed on the second and third gates; removing portions of the dielectric layer to transfer the pattern of the patterned soft mask into the dielectric layer and form first and second contact openings between the first and second gates, and third and fourth contact openings between the second and third gates; and disposing a conductive material in the contact openings.
机译:一种制造半导体器件的方法,包括在衬底上的介电层上沉积硬掩模,该介电层设置在第一,第二和第三栅极的周围;去除硬掩模的一部分以形成暴露第一,第二和第三栅极的开口;在开口内的第一,第二和第三栅极上形成图案化的软掩模,图案化的软掩模的第一部分设置在第一和第二栅极上,图案化的软掩模的第二部分设置在第二和第二栅极上第三关去除部分介电层,以将图案化的软掩模的图案转移到介电层中,并在第一和第二栅极之间形成第一和第二接触开口,以及在第二和第三栅极之间形成第三和第四接触开口;在接触孔中设置导电材料。

著录项

  • 公开/公告号US9793161B2

    专利类型

  • 公开/公告日2017-10-17

    原文格式PDF

  • 申请/专利权人 INTERNATIONAL BUSINESS MACHINES CORPORATION;

    申请/专利号US201615289542

  • 发明设计人 VEERARAGHAVAN S. BASKER;

    申请日2016-10-10

  • 分类号H01L21/768;H01L21/027;H01L21/308;

  • 国家 US

  • 入库时间 2022-08-21 13:47:09

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