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Bus arbitration apparatus provided to a bus connected to a plurality of bus masters, bus arbitration method, and computer-readable storage medium
Bus arbitration apparatus provided to a bus connected to a plurality of bus masters, bus arbitration method, and computer-readable storage medium
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机译:提供给连接到多个总线主控器的总线的总线仲裁设备,总线仲裁方法和计算机可读存储介质
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摘要
A bus arbiter (101) is provided to a bus (107). The bus (107) is connected to a plurality of bus masters, such as a CPU (410) and a serial I/F (413), to each of which a priority is given. The bus arbiter (101) changes the priorities of the plurality of bus masters at cycles determined in advance. The bus arbiter (101) receives a request signal for making a request for use of the bus (107) from at least one bus master. Based on the priorities of the respective bus masters at a time when the request signal is received, the bus arbiter (101) identifies one bus master given the highest priority among the at least one bus master that has transmitted the request signal. The bus arbiter (101) transmits a grant signal for permitting the use of the bus (107) to the identified one bus master.
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