ARCHITECTURE FOR ENSURING MONOTONICITY IN A DIGITAL-TO-ANALOG CONVERTER

摘要

A current-mode, digital-to-analog converter (DAC) configured to convert a digital word input having j bits to an analog signal. The DAC has 2^j current sources, an output node, a current divider, a first switch, and a second switch. Each of the 2^j current sources is configured to produce a current having a value I₀. The current divider has a programmable divide ratio, d, where 1/d is between 0 and 1. The first switch is configured to selectively couple 2^j-l of the 2^j current sources to the output node. One of the 2^j current sources is not coupled to the output node. The second switch is configured to selectively couple each of the 2j current sources to the current divider. This architecture ensures that the fundamental transform of input code to output current always has a slope that does not change from positive to negative or from negative to positive.