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SEMICONDUCTOR MEMORY DEVICE OUTPUTTING READY BUSY SIGNAL AND MEMORY SYSTEM INCLUDING THE SAME

机译:半导体存储器输出包括相同信号的就绪忙信号和存储器系统

摘要

A semiconductor memory device according to an embodiment of the present invention includes a peripheral circuit which is configured to control memory cells and operates in a first mode that enables communication with an external device when a chip select signal is enabled and operates in a second mode that disables communication with an external device when a chip select signal is disabled, and a ready busy signal generator which is configured to bias a ready busy line according to whether the peripheral circuit has a ready state or a busy state when the chip select signal is enabled. So, a memory system with improved operation speed can be provided.
机译:根据本发明实施例的半导体存储器件包括外围电路,该外围电路被配置为控制存储单元并且以第一模式操作,该第一模式在启用芯片选择信号时能够与外部设备进行通信,并且以第二模式操作。当禁用芯片选择信号时,禁用与外部设备的通信;当芯片选择信号使能时,就绪忙信号发生器配置为根据外围电路是处于就绪状态还是处于忙状态来偏置就绪忙线。因此,可以提供具有提高的操作速度的存储系统。

著录项

  • 公开/公告号KR20170008009A

    专利类型

  • 公开/公告日2017-01-23

    原文格式PDF

  • 申请/专利权人 SK HYNIX INC.;

    申请/专利号KR20150099188

  • 发明设计人 JEONG JAE HYEONG;KIM KWANG HYUN;

    申请日2015-07-13

  • 分类号G11C7/10;G11C16/32;G11C7/22;

  • 国家 KR

  • 入库时间 2022-08-21 13:28:18

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