AN ALLOCATION AND ISSUE STAGE FOR REORDERING A MICROINSTRUCTION SEQUENCE INTO AN OPTIMIZED MICROINSTRUCTION SEQUENCE TO IMPLEMENT AN INSTRUCTION SET AGNOSTIC RUNTIME ARCHITECTURE

摘要

A system for an agnostic runtime architecture is disclosed. The system implements a system emulation / virtualization converter, an application code converter, a system converter-a system emulation / virtualization converter, and an application code converter, and the system converter implements a system conversion process for executing code from the guest image . The system converter includes: a command fetch component for fetching an incoming micro instruction sequence; a decoding component coupled to the instruction fetch component, the decoding component receiving and decoding the fetched macro instruction sequence into a micro instruction sequence; And an allocation and issue stage for receiving the sequence and performing optimization processing by rearranging the micro instruction sequence into an optimized micro instruction sequence comprising a plurality of dependent code groups. The microprocessor pipeline is coupled to an assignment and issue stage to receive and execute the optimized micro instruction sequence. The sequence cache is coupled to an assignment and issue stage to receive and store a copy of the micro instruction sequence that is optimized for subsequent use if there is a subsequent hit in the optimized micro instruction sequence and the hardware component moves the instruction in the incoming micro instruction sequence Lt; / RTI