A tile-based processor architecture model for high efficiency embedded homogeneous multicore platforms

摘要

The present invention is directed to a processor that includes a processing element that performs a plurality of instructions in parallel and that is coupled with a point-to-point communication link, called a so-called data communication link (DCL). The instructions use a data communication link for data communication between them, and in order to realize this communication, the instructions take their operands and specify a data communication link to record their processing results. The data communication link synchronizes the execution of the instructions and allows them to explicitly manage the data they process. Communication is explicit and is used to implement storage of temporary variables that are separate from the repository of persistent variables.