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DEVICE FOR ACCELERATED CALCULATING MATRIX OF INCOMPLETE PARALLELISM

机译:不完全并行的加速计算矩阵的设备

摘要

FIELD: physics.;SUBSTANCE: to the known device containing a matrix of m rows and n columns of elements of a homogeneous medium, n unit counting blocks, a maximum finding block, an adder, a memory block, an accelerated matrix of the partial parallelism matrix containing a matrix of (ij) (i = 1, 2, …, N, j = 1, 2, …, M) of the D-triggers of the input data synchronization, the matrix from (i.j) (i = 1, 2, …, N, j = 1, 2, …, M) of OR elements, a clock generator, a frequency multiplier, 3 pulse counters, 3 decoders, 4 OR elements, 2 AND elements, and a NO-AND gate, 2 D-triggers, a shift register, a comparison element, a comparison element with zero, 2 registers, 2 multiplexers, 4-port RAM, 5 single-port RAM.;EFFECT: increasing the device speed due to the introduction of tools for the accelerated calculation of the incomplete parallelism matrix.;2 dwg
机译:领域:物理学;物质:包含一种已知设备的已知设备,该矩阵包含m行和n列均质介质的元素,n个单位计数块,最大查找块,加法器,存储块,部分矩阵的加速矩阵包含输入数据同步的D触发器的(ij)(i = 1,2,…,N,j = 1,2,…,M)矩阵的并行矩阵,来自(ij)(i = 1,2,…,N,j = 1,2,…,M)个OR元素,一个时钟发生器,一个倍频器,3个脉冲计数器,3个解码器,4个OR元素,2个AND元素和一个NO-AND门,2个D触发器,一个移位寄存器,一个比较元件,一个具有零的比较元件,2个寄存器,2个多路复用器,4端口RAM,5个单端口RAM;效果:由于引入了加速不完全并行矩阵计算的工具。; 2 dwg

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