Clock recovery through digital techniques in a coherent receiver

摘要

Digital techniques to recover clock in a coherent receiver using intradyne detection are provided. A free running oscillator clocks an analog to digital converter that is used to convert an input analog signal to digital data. The digital data is resampled using a numerically controlled oscillator clock. Phase detection is performed on the digital data after it is resampled to determine any phase offset. The numerically controlled oscillator clock is adjusted based on the phase offset. In addition, the digital data is delayed after the digital resampling operation using a digital delay element. The phase offset is also fed forward to the digital delay element.