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Method and system for efficient cache buffering in a system having parity arms to enable hardware acceleration

机译:在具有奇偶校验臂以实现硬件加速的系统中高效缓存缓冲的方法和系统

摘要

A system and method for efficient cache buffering are provided. The disclosed method includes receiving a host command from a host, extracting command information from the host command, determining an Input/Output (I/O) action to be taken in connection with the host command, determining that the I/O action spans more than one strip, and based on the I/O action spanning more than one strip, allocating a cache frame anchor for a row on-demand along with a cache frame anchor for a strip to accommodate the I/O action.
机译:提供了一种用于有效的高速缓存缓冲的系统和方法。所公开的方法包括:从主机接收主机命令;从主机命令中提取命令信息;确定要与主机命令结合进行的输入/输出(I / O)动作;确定该I / O动作跨越更多多于一个条带,并基于跨越多个条带的I / O操作,为按需分配行的缓存帧锚和一条条带的缓存帧锚分配以容纳I / O操作。

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