System and method of implementing finite difference time domain models with multiple accelerated processing components (APCs)

摘要

Embodiments of a method for implementing a finite difference time domain modeling with multiple APCs (107) are disclosed herein. The disclosed methods and systems overcome the memory capacity limitation of APCs by having each APC perform multiple timesteps on a small piece of the computational domain or data volume in a APC queued manner. The cost of transferring data between host and compute accelerator can then be amortized over multiple timesteps, greatly reducing the amount of PCI bandwidth required to sustain high propagation speeds. The APC queued nature of the algorithm achieves linear scaling of PCI throughput with increasing number of APCs, allowing the algorithm to scale up to many dozens of APCs in some embodiments.