Configuration of CGRA (COARSE-GRAINED RECONFIGURABLE ARRAY) for data flow instruction block execution in block-based data flow ISA (INSTRUCTION SET ARCHITECTURE)

摘要

It is disclosed to construct coarse-grained reconfigurable arrays (CGRAs) for data flow instruction block execution in block-based data flow instruction set architectures (ISA). In an aspect, a CGRA configuration circuit is provided, the CGRA configuration circuit comprising CGRA with an array of tiles, each of the tiles providing a functional unit and a switch. The instruction decoding circuit of the CGRA configuration circuit maps a data flow instruction in the data flow instruction block to one of the tiles of the CGRA. The instruction decoding circuit decodes the data flow instruction and generates a function control configuration for the functional unit of the mapped tile to provide the functionality of the data flow instruction. The instruction decoding circuitry further generates switch control arrangements for switches along the path of the tiles in the CGRA such that the output of the functional unit of the mapped tile is routed to each tile corresponding to the consumer instructions of the data flow instruction .;