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APPROACHES FOR INTEGRATING STT-MRAM MEMORY ARRAYS INTO A LOGIC PROCESSOR AND THE RESULTING STRUCTURES
APPROACHES FOR INTEGRATING STT-MRAM MEMORY ARRAYS INTO A LOGIC PROCESSOR AND THE RESULTING STRUCTURES
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机译:将STT-MRAM存储器阵列集成到逻辑处理器中的方法及其结果结构
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摘要
Approaches for integrating spin torque transfer magnetic random access memory (STT-MRAM) memory arrays into a logic processor, and the resulting structures, are described. In an example, a logic processor including a logic region including metal line/via pairings disposed in a dielectric layer disposed above a substrate. The logic processor also includes a spin torque transfer magnetoresistive random access memory (STT-MRAM) array including a plurality of magnetic tunnel junctions (MTJs). The MTJs are disposed in the dielectric layer.
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