A method for robust phase locked loop design

摘要

Disclosed are systems, methods, and apparatus that can improve the robustness of digital phase lock loop (PLL) circuits. The method performed by the clock generation device is the step of generating a plurality of phase shift signals, each of the plurality of phase shift signals having a phase shift with respect to a unique base clock signal within the plurality of phase shift signals. Indicating the step of generating, the step of selecting the first phase shift signal as the output signal, and the second phase shift signal when the second signal has a closer phase relationship to the reference signal than the first signal Generating a first phase control word; and refraining from selecting the second signal as an output signal while either the first signal or the second signal is in the first signaling state. Selecting the second signal as the output signal when the first signal and the second signal are in the second signaling state.