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Arithmetic processing circuit, arithmetic processing unit including arithmetic processing circuit, information processing apparatus including arithmetic processing unit, and method

机译:算术处理电路,包括算术处理电路的算术处理单元,包括算术处理单元的信息处理设备以及方法

摘要

An arithmetic processor includes a plurality of arithmetic circuits that individually execute an arithmetic operation for fixed point data; and at least one of first and second statistical information is acquired regarding a plurality of fixed point data that are results of arithmetic operation executed by the plurality of arithmetic circuits. The first statistical information is obtained by accumulating a bit pattern, which is obtained by setting a flag bit to each of bit positions corresponding to a range from a least-significant-bit position to a highest-order bit position for each of the digits corresponding to the bit positions, and the second statistical information is obtained by accumulating a bit pattern, which is obtained by setting a flag bit to each of bit positions corresponding to a range from the position of the sign bit to a lowest-order-bit position for each of the digits corresponding to the bit positions.
机译:算术处理器包括分别对定点数据执行算术运算的多个算术电路。并且获取关于多个定点数据的第一和第二统计信息中的至少一个,所述多个定点数据是由多个算术电路执行的算术运算的结果。通过累积位模式来获得第一统计信息,该位模式是通过将标志位设置到与对应于每个数字的从最低有效位位置到最高顺序位位置的范围相对应的每个位位置而获得的。通过累积位模式获得第二统计信息,该位模式是通过将标志位设置到与从符号位的位置到最低位的位置的范围相对应的每个位位置而获得的对于与位位置相对应的每个数字。

著录项

  • 公开/公告号JP6540770B2

    专利类型

  • 公开/公告日2019-07-10

    原文格式PDF

  • 申请/专利权人 富士通株式会社;

    申请/专利号JP20170200898

  • 发明设计人 依田 勝洋;伊藤 真紀子;

    申请日2017-10-17

  • 分类号G06F9/315;G06F7/499;G06G7/60;

  • 国家 JP

  • 入库时间 2022-08-21 12:19:33

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