首页> 外国专利> Multi-value numerical discriminant circuit, multi-value OR logic discriminant circuit based on the principle of fuse algebra, and multi-level AND logic discriminant circuit based on the principle of fuse algebra

Multi-value numerical discriminant circuit, multi-value OR logic discriminant circuit based on the principle of fuse algebra, and multi-level AND logic discriminant circuit based on the principle of fuse algebra

机译:基于保险丝代数原理的多值数值判别电路,多值或逻辑判别电路,以及基于保险丝代数原理的多电平AND逻辑判别电路

摘要

PROBLEM TO BE SOLVED: To provide a circuit for distinguishing a numerical value for multi values, using no resistor between input and output terminals, capable of being configured only by FETs performing a switching operation, and capable of being used also for a multivalued logic circuit.SOLUTION: In a circuit for distinguishing a numerical value for multi values, one two-valued CMOS NOT circuit is provided between a power line Vm+1 and a power line Vm and between the power line Vm and a power line Vm-1, and both input terminals thereof are connected to be an input terminal Tin. A part between a gate and a source of a normally off NMOS 96 is connected between both of the output terminals, the NMOS 96 having a threshold voltage Vth 96 that has an absolute value of less than a voltage between a power source potential Vm+1 and a power source potential Vm-1 and more than a voltage between the power source potential Vm+1 and a power source potential Vm and a voltage between the power source potential Vm and the power source potential Vm-1, the drain terminal of the NMOS 96 is used as an output terminal Tout, and it is distinguished whether an input signal potential of the input terminal corresponds to an integer m.SELECTED DRAWING: Figure 1
机译:解决的问题:提供一种用于在输入和输出端子之间不使用电阻器的情况下,区分多个值的电路的电路,该电路只能由执行开关操作的FET构成,并且还可以用于多值逻辑电路解决方案:在用于区分多个数值的电路中,在电源线Vm + 1和电源线Vm之间以及在电源线Vm和电源线Vm-1之间提供一个二值CMOS NOT电路,其两个输入端子被连接为输入端子Tin。常闭NMOS 96的栅极和源极之间的部分连接在两个输出端子之间,NMOS 96具有阈值电压Vth 96,该阈值电压Vth 96的绝对值小于电源电势Vm + 1之间的电压。电源电位Vm-1,电源电位Vm + 1与电源电位Vm之间的电压以及电源电位Vm与电源电位Vm-1之间的电压,以及漏极电位。 NMOS 96用作输出端子Tout,并区分输入端子的输入信号电势是否对应于整数m。

著录项

  • 公开/公告号JP6524374B2

    专利类型

  • 公开/公告日2019-06-05

    原文格式PDF

  • 申请/专利权人 鈴木 利康;

    申请/专利号JP20150142084

  • 发明设计人 鈴木 利康;

    申请日2015-07-16

  • 分类号H03K19/20;

  • 国家 JP

  • 入库时间 2022-08-21 12:18:57

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