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HIGH-SPEED AND LOW-POWER PIPELINED ADC USING DYNAMIC REFERENCE VOLTAGE AND 2-STAGE SAMPLE-AND-HOLD
HIGH-SPEED AND LOW-POWER PIPELINED ADC USING DYNAMIC REFERENCE VOLTAGE AND 2-STAGE SAMPLE-AND-HOLD
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机译:利用动态参考电压和2阶采样保持的高速低功耗流水线ADC
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摘要
Disclosed is a high-speed and low-power pipelined analog-digital converter (ADC) using a dynamic reference voltage and a 2-stage S/H. The pipelined ADC includes a 2-stage sample-and-hold (S/H) configured to secure a conversion time corresponding to a clock cycle per stage and to apply only a buffer to an input signal path, a reference voltage generator configured to receive the output of the D flip-flop of a previous stage as an input signal and to generate a required reference voltage during a half cycle of a sample frequency, and a comparator configured to include a linear transconductor (LT), a rail-to-rail latch (R2R) and a D flip-flop and to generate the output of the ADC and input to the reference voltage generator of a next stage for generating a reference voltage using the output of the D flip-flop.
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