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VLSI Layouts of Fully Connected Generalized and Pyramid Networks with Locality Exploitation

机译:局部开发的全连接式金字塔网络的VLSI布局

摘要

VLSI layouts of generalized multi-stage and pyramid networks for broadcast, unicast and multicast connections are presented using only horizontal and vertical links with spacial locality exploitation. The VLSI layouts employ shuffle exchange links where outlet links of cross links from switches in a stage in one sub-integrated circuit block are connected to inlet links of switches in the succeeding stage in another sub-integrated circuit block so that said cross links are either vertical links or horizontal and vice versa. Furthermore the shuffle exchange links are employed between different sub-integrated circuit blocks so that spacially nearer sub-integrated circuit blocks are connected with shorter links compared to the shuffle exchange links between spacially farther sub-integrated circuit blocks. In one embodiment the sub-integrated circuit blocks are arranged in a hypercube arrangement in a two-dimensional plane. The VLSI layouts exploit the benefits of significantly lower cross points, lower signal latency, lower power and full connectivity with significantly fast compilation.;The VLSI layouts with spacial locality exploitation presented are applicable to generalized multi-stage and pyramid networks, generalized folded multi-stage and pyramid networks, generalized butterfly fat tree and pyramid networks, generalized multi-link multi-stage and pyramid networks, generalized folded multi-link multi-stage and pyramid networks, generalized multi-link butterfly fat tree and pyramid networks, generalized hypercube networks, and generalized cube connected cycles networks for speedup of s≥1. The embodiments of VLSI layouts are useful in wide target applications such as FPGAs, CPLDs, pSoCs, ASIC placement and route tools, networking applications, parallel & distributed computing, and reconfigurable computing.
机译:广播,单播和多播连接的通用多级和金字塔网络的VLSI布局仅使用水平和垂直链接以及空间位置利用来呈现。 VLSI布局采用混洗交换链路,其中一个子集成电路块中的一个阶段中的开关的交叉链路的出口链路连接到另一子集成电路块中的下一个阶段的交换机的入口链路,因此所述交叉链路可以是垂直链接或水平链接,反之亦然。此外,在不同的子集成电路块之间采用混洗交换链路,从而与在空间上较远的子集成电路块之间的混洗交换链路相比,在空间上较近的子集成电路块以较短的链路连接。在一个实施例中,子集成电路块以超立方体布置布置在二维平面中。 VLSI布局具有显着降低交叉点,降低信号延迟,降低功耗和完全连接的优势,并且编译速度显着加快。阶段和金字塔网络,广义蝴蝶胖树和金字塔网络,广义多链接多阶段和金字塔网络,广义折叠多链接多阶段和金字塔网络,广义多链接蝴蝶胖树和金字塔网络,广义超立方体网络和广义立方连接的循环网络,以加速s≥1。 VLSI布局的实施例在诸如FPGA,CPLD,pSoC,ASIC放置和路由工具,网络应用,并行和分布式计算以及可重构计算的广泛目标应用中有用。

著录项

  • 公开/公告号US2019036844A1

    专利类型

  • 公开/公告日2019-01-31

    原文格式PDF

  • 申请/专利权人 VENKAT KONDA;

    申请/专利号US201816029645

  • 发明设计人 VENKAT KONDA;

    申请日2018-07-08

  • 分类号H04L12/933;H04L12/50;G06F17/50;

  • 国家 US

  • 入库时间 2022-08-21 12:04:40

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