IP NUCLEUS, ARCHITECTURE COMPRISING AN IP NUCLEUS AND AN IP NUCLEUS DESIGN PROCEDURE (Machine-translation by Google Translate, not legally binding)

摘要

IP core, architecture comprising an IP core and procedure for designing an IP core. A configurable and programmable IP processing core for the computation of a plurality of matrix products, in which both the data to be processed and the results obtained are serially transferred, comprising: The IP core comprises: a data entry block for providing a set of vectors representing a first and a second matrix whose product is to be computed, wherein said data entry block comprises: a first sub-block and a second sub-block; a memory block comprising N memory elements associated with a respective output of said second sub-block of the data entry block; a matrix multiplier-vector in a fixed point to implement a multiplication-accumulation operation; a block comprising at least one activation function configured to be applied to the output of said fixed-vector matrix-vector multiplier block; a block for storing the outputs of the at least one activation function and for reading the outputs of said storage components; a FIFO block and a data output block comprising a row counter and a column counter. System on chip comprising at least one IP.FPGA core comprising at least one IP core. Procedure for designing an IP core. (Machine-translation by Google Translate, not legally binding)