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CPU HMC HMC CPU side and HMC side HMC Control Apparatus and Method for Low Power Mode and Recording Medium Thereof
CPU HMC HMC CPU side and HMC side HMC Control Apparatus and Method for Low Power Mode and Recording Medium Thereof
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机译:CPU HMC HMC CPU侧和HMC侧HMC控制装置以及低功率模式及其记录介质的方法
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摘要
The present invention relates to devices for controlling a hybrid memory cube (HMC) on the side of a central processing unit (CPU) and on the side of the HMC in a low-power mode, a method for the same, and a recording medium thereof. The HMC control device on the CPU side includes multiple link units. Each of the link units includes: a link master which stores request packets of the CPU to a request buffer and transmits the request packets to the HMC control device on the HMC side in accordance with the stored sequence; and a link slave which stores the request packets transmitted from the HMC control device on the HMC side to a response buffer and transmits the request packets to the CPU in accordance with the storage order. The link master is switched to standby mode which does not receive any more request packets from the CPU when a low-power mode request is generated by the CPU. The link master generates check packets only when the buffers are empty after checking the buffers in standby mode to transmit the check packets to the HMC control device on the HMC side. The link master is switched to sleep mode when receiving the check packets from the HMC control device on the HMC side. The devices enable a stable low-power mode switching operation without packet loss.
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