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SELF-TESTING OF A PHASE-LOCKED LOOP USING A PSEUDO-RANDOM NOISE

机译:使用伪随机噪声对锁相环进行自检

摘要

An apparatus includes signal control circuitry, a phase-locked loop (PLL), and a correlation circuit. The signal control circuitry provides a reference clock signal carrying pseudo-random phase noise and as derived from an application clock signal and pseudo-random noise. The PLL, responsive to the reference clock signal carrying the pseudo-random phase noise, provides an output signal that is related to the phase of the reference clock signal. The correlation circuit self-tests the PLL by cross-correlating a signal corresponding to the output signal from the phase detector with the pseudo-random noise and, in response, by assessing results of the cross-correlation relative to a known threshold indicative of a performance level of the PLL.
机译:一种设备,包括信号控制电路,锁相环(PLL)和相关电路。信号控制电路提供参考时钟信号,该参考时钟信号携带伪随机相位噪声,并从应用时钟信号和伪随机噪声中得出。 PLL响应于携带伪随机相位噪声的参考时钟信号,提供与参考时钟信号的相位有关的输出信号。相关电路通过将与来自相位检测器的输出信号相对应的信号与伪随机噪声进行互相关,并作为响应,通过评估互相关的结果相对于表示阈值的已知阈值,对PLL进行自检。 PLL的性能水平。

著录项

  • 公开/公告号EP3598646A1

    专利类型

  • 公开/公告日2020-01-22

    原文格式PDF

  • 申请/专利权人 NXP B.V.;

    申请/专利号EP20190184460

  • 发明设计人 SCHAT JAN-PETER;MOEHLMANN ULRICH;

    申请日2019-07-04

  • 分类号H03L7/08;

  • 国家 EP

  • 入库时间 2022-08-21 11:38:40

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