首页> 外国专利> Coset probability based majority-logic decoding for non-binary LDPC codes

Coset probability based majority-logic decoding for non-binary LDPC codes

机译:基于陪集概率的非二进制LDPC码多数逻辑解码

摘要

A method for iteratively decoding read bits in a solid state storage device. The read bits are encoded with a Q-ary LDPC code defined over a binary-extension Galois field GF(2r) and having length N. The method comprises determining a binary Tanner graph of the Q-ary LDPC code based on a Q-ary Tanner graph of the Q-ary LDPC code, and based on a binary coset representation of the Galois field GF(2r). The binary Tanner graph comprises, for each Q-ary variable node/Q-ary check node pair of the Q-ary Tanner graph, (2r-1) binary variable nodes each one being associated with a respective one of said cosets; (2r-1-r) binary parity-check nodes each one being connected to one or more of said (2r-1) binary variable nodes according to said binary coset representation of the Galois field GF(2r), wherein each binary parity-check node corresponds to a respective parity-check equation associated with a first parity-check matrix that results from said binary coset representation, and (2r-1) binary check nodes each one being connected to a respective one of said (2r-1) binary variable nodes according to a second parity-check matrix defining the Q-ary LDPC code. The method further comprises, based on a Majority-Logic decoding algorithm, mapping the read bits into N symbols each one including, for each bit thereof, a bit value and a reliability thereof, and providing each symbol of said N symbols to a respective Q-ary variable node, wherein each bit of said each symbol is provided to a respective one of the (2r-1) binary variable nodes of said respective Q-ary variable node. The method also comprises, based on the Majority-Logic decoding algorithm, iteratively performing the following steps: i) at each binary check node, determining a first bit estimate and a first bit reliability of each bit of the respective symbol according to, respectively, a second bit estimate and a second bit reliability of that bit that are determined at each binary variable node connected to that binary check node, and ii) at each binary variable node, updating the second bit estimate and the second bit reliability of each bit of the respective symbol based on the first bit estimate and the first bit reliability of that bit determined at each binary check node connected to that binary variable node, and based on the parity-check equation associated with the first parity-check matrix and corresponding to the parity-check node connected to that binary variable node.
机译:一种用于对固态存储设备中的读取位进行迭代解码的方法。使用在二进制扩展Galois字段GF(2 r )上定义的Q元LDPC码对读取的位进行编码,并且长度为N。该方法包括确定Q元的二进制Tanner图。 LDPC代码基于Q元LDPC码的Q元Tanner图,并基于Galois字段GF(2 r )的二进制陪集表示。对于Q元Tanner图的每个Q元变量节点/ Q元校验节点对,二进制Tanner图包括(2 r -1)个二进制变量节点,每个节点与一个所述陪同者各自; (2 r -1- r )个二进制奇偶校验节点,每个节点都与一个或多个所述(2 r -1)连接根据Galois字段GF(2 r )的所述二进制陪集表示的二进制变量节点,其中每个二进制奇偶校验节点对应于与第一奇偶校验矩阵关联的各个奇偶校验方程,所述二进制陪集表示的结果,以及(2 r -1)个二进制校验节点,每个节点分别与所述(2 r -1)个二进制变量节点之一连接根据定义Q元LDPC码的第二奇偶校验矩阵。该方法进一步包括基于多数逻辑解码算法,将读取的比特映射到N个符号,每个符号包括针对其每个比特的比特值及其可靠性,以及将所述N个符号的每个符号提供给相应的Q。一元变量节点,其中所述每个符号的每一比特被提供给所述各个Q元变量节点的(2Supr-1)个二进制变量节点中的相应一个。该方法还包括基于多数逻辑解码算法,迭代地执行以下步骤:i)在每个二进制校验节点处,分别根据分别确定各个符号的每个比特的第一比特估计和第一比特可靠性。在连接到该二进制校验节点的每个二进制变量节点处确定的该比特的第二比特估计和第二比特可靠性,以及ii)在每个二进制变量节点处确定,更新该比特的第二比特估计和第二比特可靠性。基于在与该二进制变量节点连接的每个二进制校验节点处确定的该比特的第一比特估计和该比特的第一比特可靠性,以及基于与第一奇偶校验矩阵相关联并且对应于该奇偶校验矩阵的奇偶校验等式,相应符号连接到该二进制变量节点的奇偶校验节点。

著录项

  • 公开/公告号US10790854B2

    专利类型

  • 公开/公告日2020-09-29

    原文格式PDF

  • 申请/专利权人 NANDEXT S.R.L.;

    申请/专利号US201916250921

  • 发明设计人 EMANUELE VITERBO;VIDURANGA WIJEKOON;

    申请日2019-01-17

  • 分类号H03M13/11;H03M13/43;H03M13;

  • 国家 US

  • 入库时间 2022-08-21 11:29:07

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