首页> 外国专利> CIRCUITRY AND METHODOLOGY BENEFITTING FROM REDUCED GATE LOSS

CIRCUITRY AND METHODOLOGY BENEFITTING FROM REDUCED GATE LOSS

机译:减少门损耗所带来的电路和方法学好处

摘要

In specific examples, aspects are directed towards eliminating, mitigating or reducing gate loss in circuits including, for example, WBG power devices. One such example is directed towards an apparatus including first and second types of field-effect transistor (FET), where the first type is characterized as being a normally-on FET in a switching-circuit operation with a high-voltage rating, and the second type of FET is characterized as being a normally-off FET in a switching-circuit operation with a voltage rating that is much less than the high-voltage rating of the first type of FET circuit. The FET are arranged in a cascode manner so that, in response to a switching control signal received by the second type of FET circuit, the second type of FET circuit is active to drive the first type of FET.
机译:在特定示例中,各方面旨在消除,减轻或减少包括例如WBG功率器件的电路中的栅极损耗。一个这样的示例针对包括第一和第二类型的场效应晶体管(FET)的设备,其中第一类型的特征在于在具有高额定电压的开关电路操作中为常开FET,并且第二种类型的FET的特征在于它是开关电路操作中的常关FET,其额定电压远小于第一种FET电路的高压额定值。 FET以共源共栅方式布置,使得响应于由第二类型的FET电路接收到的开关控制信号,第二类型的FET电路被激活以驱动第一类型的FET。

著录项

相似文献

  • 专利
  • 外文文献
  • 中文文献
获取专利

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号