Verification of Hardware Design for Data Transformation Pipeline with Equivalent Data Transformation Element Output Constraint

摘要

Methods and systems for verifying, via formal verification, a hardware design for a data transformation pipeline comprising one or more data transformation elements that perform a data transformation on one or more inputs, wherein the formal verification is performed under conditions that simplify the data transformations calculations that the formal verification tool has to perform. In one embodiment the hardware design for the data transformation pipeline is verified by formally verifying that the output of an instantiation of the hardware design produces the same output as an instantiation of a hardware design for another data transformation pipeline for a predetermined set of transactions under a constraint that substantially equivalent data transformation elements between the data transformation pipelines produce the same output(s) in response to the same input(s).