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METHOD TO VERTICALLY ROUTE A LOGIC CELL INCORPORATING STACKED TRANSISTORS IN A THREE DIMENSIONAL LOGIC DEVICE
METHOD TO VERTICALLY ROUTE A LOGIC CELL INCORPORATING STACKED TRANSISTORS IN A THREE DIMENSIONAL LOGIC DEVICE
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机译:在三维三维逻辑设备中垂直路由包含堆叠晶体管的逻辑单元的方法
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摘要
A semiconductor device includes: a substrate having a surface, the surface being planar; a first logic gate provided on the substrate and comprising a first field effect transistor (FET) having a first channel, and a first pair of source-drain regions; a second logic gate stacked over the first logic gate along a vertical direction perpendicular to the surface of the substrate, the second logic gate comprising a second FET having a second channel, and a second pair of source-drain regions; and a contact electrically connecting a source-drain region of the first FET to a source-drain region of the second FET such that at least a portion of current flowing between the first and second logic gate will flow along said vertical direction.
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