DUT FPGA A TEST ARCHITECTURE HAVING MULTIPLE FPGA BASED HARDWARE ACCELERATOR BLOCKS FOR TESTING MULTIPLE DUTS INDEPENDENTLY

摘要

Automated Test Equipment (ATE) is presented that is capable of performing tests of semiconductor devices. The ATE includes a computer system that includes a system controller communicatively coupled to the tester processor. The system controller is operable to send instructions to the processor, the processor being operable to generate commands and data from the instructions to coordinate a test of a plurality of Device Under Tests (DUTs). The ATE further includes a plurality of FPGA components communicatively coupled to the processor via a bus. Each FPGA component includes at least one hardware accelerator circuit operable to internally generate commands and data transparently from a processor to test one of the DUTs. In addition, the tester processor is configured to operate in one of several functional modes, the functional modes being configured to assign functionality for generating commands and data between the processor and the FPGA component.