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A surface-potential-based compact model for partially-depleted silicon-on-insulator MOSFETs

机译:基于表面电位的紧凑型模型,用于部分耗尽的绝缘体上硅mOsFET

摘要

With the continuous scaling of CMOS technologies, Silicon-on-Insulator (SOI) technologies have become more competitive compared to bulk, due to their lower parasitic capacitances and leakage currents. The shift towards high frequency, low power circuitry, coupled with the increased maturity of SOI process technologies, have made SOI a genuinely costeffective solution for leading edge applications. The original STAG2 model, developed at the University of Southampton, UK, was among the first compact circuit simulation models to specifically model the behaviour of Partially-Depleted (PD) SOI devices. STAG2 was a robust, surface-potential based compact model, employing closed-form equations to minimise simulation times for large circuits. It was able to simulate circuits in DC, small signal, and transient modes, and particular care was taken to ensure that convergence problems were kept to a minimum. In this thesis, the ongoing development of the STAG model, culminating in the release of a new version, STAG3, is described. STAG3 is intended to make the STAG model applicable to process technologies down to 100nm. To this end, a number of major model improvements were undertaken, including: a new core surface potential model, new vertical and lateral field mobility models, quantum mechanical models, the ability to model non-uniform vertical doping profiles, and other miscellaneous effects relevant to deep submicron devices such as polysilicon depletion, velocity overshoot, and the reverse short channel effect.As with the previous versions of STAG, emphasis has been placed on ensuring that model equations are numerically robust, as well as closed-form wherever possible, in order to minimise convergence problems and circuit simulation times. The STAG3 model has been evaluated with devices manufactured in PD-SOI technologies down to 0.25?m, and was found to give good matching to experimental data across a range of device sizes and biases, whilst requiring only a single set of model parameters.
机译:随着CMOS技术的不断发展,由于其寄生电容和泄漏电流较低,因此绝缘体上硅(SOI)技术与大宗产品相比更具竞争力。向高频,低功率电路的转变,再加上SOI工艺技术的日益成熟,已经使SOI成为领先应用的真正具有成本效益的解决方案。由英国南安普敦大学开发的原始STAG2模型是专门针对部分耗尽(PD)SOI器件行为进行建模的首批紧凑型电路仿真模型之一。 STAG2是一个鲁棒的,基于表面电势的紧凑型模型,采用闭式方程式以最大程度地减少大型电路的仿真时间。它能够在DC,小信号和瞬态模式下仿真电路,并特别注意确保将收敛问题保持在最低限度。在本文中,描述了STAG模型的持续发展,并最终发布了新版本STAG3。 STAG3旨在使STAG模型适用于100nm以下的工艺技术。为此,进行了许多主要的模型改进,包括:新的核心表面势模型,新的垂直和横向场迁移率模型,量子力学模型,对非均匀垂直掺杂分布进行建模的能力以及其他与之相关的其他影响对于较深的亚微米器件,例如多晶硅耗尽,速度过冲和反向短沟道效应。与以前的STAG版本一样,重点一直放在确保模型方程在数值上是稳健的,并且在可能的情况下尽可能采用封闭形式。为了最小化收敛问题和电路仿真时间。 STAG3模型已经用PD-SOI技术制造的器件(低至0.25μm)进行了评估,发现可以在一系列器件尺寸和偏置范围内与实验数据很好地匹配,而只需要一组模型参数。

著录项

  • 作者

    Benson James;

  • 作者单位
  • 年度 2009
  • 总页数
  • 原文格式 PDF
  • 正文语种 {"code":"en","name":"English","id":9}
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