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Tcad-based statistical analysis and modeling of gate line-edge roughness effect on nano-scale mos transistor performance and scaling

机译：基于Tcad的栅极线边缘粗糙度统计分析和建模对纳米级mos晶体管性能和缩放的影响

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Seong-dong Kim; Hideyuki Wada; Jason C. S. Woo; Senior Member;
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年度 2004
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1. TCAD-Based Statistical Analysis and Modeling of Gate Line-Edge Roughness Effect on Nanoscale MOS Transistor Performance and Scaling [J] . Seong-Dong Kim, Hideyuki Wada, Jason C. S. Woo IEEE Transactions on Semiconductor Manufacturing . 2004,第2期

机译：基于TCAD的栅极线边缘粗糙度对纳米级MOS晶体管性能和缩放比例影响的统计分析和建模
2. TCAD-based statistical analysis and modeling of gate line-edge roughness effect on nanoscale MOS transistor performance and scaling [J] . Seong-Dong Kim, Wada H., Woo J.C.S. IEEE Transactions on Semiconductor Manufacturing . 2004,第2期

机译：基于TCAD的栅极线边缘粗糙度对纳米MOS晶体管性能和缩放比例影响的统计分析和建模
3. Semi-analytical modeling of high performance nano-scale complementary logic gates utilizing ballistic carbon nanotube transistors [J] . Mohammad Khaleqi Qaleh Jooq, Ali Mir, Satar Mirzakuchaki, Physica, E. Low-dimensional systems & nanostructures . 2018,第期

机译：采用弹道碳纳米管晶体管高性能纳米级互补逻辑门的半分析模型
4. Design of High Performance Dual-Gate Nano-Scale In_(0.55)Ga_(0.45)As Transistor with modified Substrate Geometry [C] . Baldeo Sharan Sharma, M. S. Bhat IEEE Annual Ubiquitous Computing, Electronics amp;amp;amp; Mobile Communication Conference . 2017

机译：具有改进的基板几何形状的高性能双门纳米尺度IN_（0.55）GA_（0.45）设计为晶体管
5. Advanced III-V / Si nano-scale transistors and contacts: Modeling and analysis. [D] . Park, Seung Hyun. 2014

机译：先进的III-V / Si纳米级晶体管和触点：建模和分析。
6. Meta-analysis of prediction model performance across multiplestudies: Which scale helps ensure between-study normality for theC-statistic and calibration measures? [O] . Kym IE Snell, Joie Ensor, Thomas PA Debray, -1

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7. Graph Modeling for Static Timing Analysis at Transistor Level in Nano-Scale CMOS Circuits [O] . Abdoul Rjoub, Almotasem Bellah Alajlouni, Hassan Almanasrah 2013

机译：纳米级CMOS电路中晶体管级静态时序分析的图形建模

Tcad-based statistical analysis and modeling of gate line-edge roughness effect on nano-scale mos transistor performance and scaling

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