Design and implementation of frequency synthesizers for 3-10 ghz mulitband ofdm uwb communication

摘要

The allocation of frequency spectrum by the FCC for Ultra Wideband (UWB)communications in the 3.1-10.6 GHz has paved the path for very high data rate Gb/swireless communications. Frequency synthesis in these communication systems involvesgreat challenges such as high frequency and wideband operation in addition to stringentrequirements on frequency hopping time and coexistence with other wireless standards.This research proposes frequency generation schemes for such radio systems and theirintegrated implementations in silicon based technologies. Special emphasis is placed onefficient frequency planning and other system level considerations for building compactand practical systems for carrier frequency generation in an integrated UWB radio.This work proposes a frequency band plan for multiband OFDM based UWBradios in the 3.1-10.6 GHz range. Based on this frequency plan, two 11-band frequencysynthesizers are designed, implemented and tested making them one of the firstfrequency synthesizers for UWB covering 78% of the licensed spectrum. The circuits areimplemented in 0.25?m SiGe BiCMOS and the architectures are based on a single VCO at a fixed frequency followed by an array of dividers, multiplexers and single sideband(SSB) mixers to generate the 11 required bands in quadrature with fast hopping in muchless than 9.5 ns. One of the synthesizers is integrated and tested as part of a 3-10 GHzpackaged receiver. It draws 80 mA current from a 2.5 V supply and occupies an area of2.25 mm2.Finally, an architecture for a UWB synthesizer is proposed that is based on asingle multiband quadrature VCO, a programmable integer divider with 50% duty cycleand a single sideband mixer. A frequency band plan is proposed that greatly relaxes thetuning range requirement of the multiband VCO and leads to a very digitally intensivearchitecture for wideband frequency synthesis suitable for implementation in deepsubmicron CMOS processes. A design in 130nm CMOS occupies less than 1 mm2 whileconsuming 90 mW. This architecture provides an efficient solution in terms of area andpower consumption with very low complexity.