首页> 外文OA文献 >Structural Design of Three-dimensionally Stacked Silicon Chips Mounted by Flip Chip Technology for Minimizing Their Residual Stress

【2h】

Structural Design of Three-dimensionally Stacked Silicon Chips Mounted by Flip Chip Technology for Minimizing Their Residual Stress

机译：倒装芯片技术安装三维堆叠硅芯片的结构设计，以使其残余应力最小化

代理获取

本网站仅为用户提供外文OA文献查询和代理获取服务，本网站没有原文。下单后我们将采用程序或人工为您竭诚获取高质量的原文，但由于OA文献来源多样且变更频繁，仍可能出现获取不到、文献不完整或与标题不符等情况，如果获取不到我们将提供退款服务。请知悉。

页面导航

著录项
相似文献
相关主题

著录项

作者
Nobuki Ueta; Takuya Sasaki; Hideo Miura;
展开▼
作者单位

展开▼
年度 2009
总页数
原文格式 PDF
正文语种
中图分类

相似文献

外文文献
专利

1. Comparison of the properties of AlGaInN light-emitting diode chips of vertical and flip-chip design using silicon as the a submount [J] . Markov L.K., Smirnova I.P., Pavlyuchenko A.S., Semiconductors . 2013,第3期

机译：以硅为基底的垂直和倒装芯片设计的AlGaInN发光二极管芯片的性能比较
2. Thermal stress analysis and design optimization of direct chip attach (DCA) and chip scale package (CSP) in flip chip technology [J] . D. S. Liu, C. Y. Ni, T. C. Tsay, Engineering Optimization . 2002,第6期

机译：倒装芯片技术中直接芯片连接（DCA）和芯片级封装（CSP）的热应力分析和设计优化
3. Minimization of the Local Residual Stress in 3D Flip Chip Structures by Optimizing the Mechanical Properties of Electroplated Materials and the Alignment Structure of TSVs and Fine Bumps [J] . Kota Nakahira, Hironori Tago, Fumiaki Endo, Journal of Electronic Packaging . 2012,第2期

机译：通过优化电镀材料的机械性能以及TSV和细小凸块的对准结构，使3D倒装芯片结构中的局部残余应力最小化
4. DOMINANT STRUCTURAL FACTORS OF LOCAL RESIDUAL STRESS IN THREE-DIMENSIONALLY STACKED LSI CHIPS MOUNTED USING FLIP CHIP TECHNOLOGY [C] . Nobuki Ueta, Hideo Miura ASME(American Society of Mechanical Engineers) InterPack Conference 2007(IPACK2007) . 2007

机译：倒装芯片安装三维叠层LSI芯片局部残余应力的支配结构因素
5. Underfill adhesion characteristics, residual stresses and analysis of thermal stresses in flip-chip packages. [D] . Sham, Man-Lung. 2003

机译：倒装芯片封装中的底部填充粘合特性，残余应力和热应力分析。
6. Co-Design Method and Wafer-Level Packaging Technique of Thin-Film Flexible Antenna and Silicon CMOS Rectifier Chips for Wireless-Powered Neural Interface Systems [O] . Kenji Okabe, Horagodage Prabhath Jeewan, Shota Yamagiwa, 2015

机译：用于无线供电的神经接口系统的薄膜柔性天线和硅CMOS整流器芯片的协同设计方法和晶圆级封装技术
7. Thermo-Viscoelastic Analysis of Warp Deformation and Residual Stress for Laminated Bodies of Flip-Chip Mounted LSI Device. [O] . Shozo NAKAMURA, Koji SERIZAWA 1997

机译：倒装芯片安装LSI装置的叠层体脉冲变形和残余应力的热粘弹性分析。
8. Stresses from flip-chip assembly and underfill; measurements with the ATC4.1 assembly test chip and analysis by finite element method [R] . Peterson, D. W., Sweet, J. N., Burchett, S. N., 1996

机译：倒装芯片组装和底部填充应力;用aTC4.1装配测试芯片测量并用有限元法分析

Structural Design of Three-dimensionally Stacked Silicon Chips Mounted by Flip Chip Technology for Minimizing Their Residual Stress

著录项

相似文献

相关主题

期刊订阅