Logic Decomposition of Asynchronous Circuits Using Unfoldings

摘要

A technique for logic decomposition of asynchronous circuits which works on STG unfolding prefixes rather than state graphs is proposed. It retains all the advantages of the state space based approach, such as the possibility of multiway acknowledgement, latch utilization and highly optimized circuits. Moreover, it significantly alleviates the state space explosion, and thus has superior memory consumption and runtime.