Systeme Memoire pour Architecture Multiprocesseur sur Bus Unique. Application au Systeme SCQM (Memory Systems for Single Bus Multiprocessor Architecture. Application to the SCQM System)

摘要

The implementation of associated records to translate processor addresses in a single virtual memory space, the characterization and implementation of a single bus in a multiprocessor environment, the development of an algorithm to update the central memory from machine fore-memories, and the analysis of possible variants for MIMD strongly coupled multiprocessor architectures are discussed. The choices made are justified by experimental simulations.