Residue Arithmetic for Fault-Tolerant Multiplier: The Residue Generator

摘要

Detection and correction of errors due to hardware faults in a VLSI multiplier are treated, with regard to silicon area and time performances. Due to its regularity, modularity, and carry-free properties, Residue Number System (RNS) is considered to design a fault tolerant multiplier, in which the control and correction network avoid intrinsic disadvantages of TMR. Great compactness of additional RNS multipliers is partially masked by the area the binary-residue circuit uses, so careful design of these circuits is required. To achieve a low degradation in performances with respect to the nonfault tolerant multiplier and to contain silicon area, there are two possibilities: choose the best triple of bases for a given number of bits, to be used in the RNS control and correcting network; and choose the suitable binary to residue conversion circuit, considering area and delay.