Design of LPM Address Generators Using Multiple LUT Cascades on FPGAs

摘要

We propose the multiple LUT cascade as a means to configure an n- input LPM (Longest Prefix Match) address generator commonly used in routers to determine the output port given an address. The LPM address generator accepts n- bit addresses which it matches against k stored prefixes. We implement our design on a Xilinx Spartan-3 FPGA for n = 32 and k = 504 tilde 511. Also, we compare our design to a Xilinx proprietary TCAM (ternary content-addressable memory) design and to another design we propose as a likely solution to this problem. Our best multiple LUT cascade implementation has 5.17 times more throughput, 40.71 times more throughput/area and is 2.97 times more efficient in terms of area-delay product than Xilinx s proprietary design, but its area is only 15% of Xilinx s design. Furthermore, we derive a method to determine the optimum configuration of the multiple LUT cascade on an FPGA.