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Systematic Design Method for Two-Variable Numeric Function Generators Using Multiple-Valued Decision Diagrams.

机译:基于多值决策图的双变量数值函数发生器系统设计方法。

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This paper proposes a high-speed architecture to realize two- variable numeric functions. It represents the given function as an edge-valued multiple-valued decision diagram (EVMDD), and shows a systematic design method based on the EVMDD. To achieve a design, we characterize a numeric function f by the values of l and p for which f is an l-restricted Mp-monotone increasing function. Here, l is a measure of subfunctions of f and p is a measure of the rate at which f increases with an increase in the dependent variable. For the special case of an EVMDD, the EVBDD, we show an upper bound on the number of nodes needed to realize an l-restricted Mp-monotone increasing function. Experimental results show that all of the two-variable numeric functions considered in this paper can be converted into an l-restricted Mp-monotone increasing function with p = 1 or 3. Thus, they can be compactly realized by EVBDDs. Since EVMDDs have shorter paths and smaller memory size than EVBDDs, EVMDDs can produce fast and compact NFGs. key words: two-variable numeric function generators (NFGs), edge-valued multiple-valued decision diagrams (EVMDDs), edge-valued binary decision diagrams (EVBDDs), graph-based representation of numeric functions, programmable memory-based architecture.

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