On the Performance of an Imperfectly-Implemented Symmetrical Differential Detector.

摘要

An investigation into the performance of a differential detector (DD) used to demodulate a carrier which is modulated differentially with plus and minus ninety degree phase shifts by a bit stream is presented. The plus-minus ninety degree (symmetrical) DD is analyzed both analytically and experimentally in terms of the effects of bit synchronization error, carrier frequency uncertainty, and signal bandlimiting and hardlimiting. In all cases the performance of the symmetrical DD is compared to that for the conventional (zero-one hundred eighty degree) DD. An expression for the performance of both DD's when the noise at the receiver input is white and Gaussian distributed, the bit synchronization error is Gaussian distributed, and the carrier frequency estimate is constant as a function of time is derived. The effects of bandlimiting and hardlimiting on the signal in both the frequency and time domain is considered. The circuitry for generating the symmetrical differential phase shift keyed (DPSK) signal is presented and an analysis of the circuitry required for bit synchronization is performed. The results presented provide both the motive and the means for implementing symmetrical DPSK and DD in present and future communication systems where severe bandlimiting and hardlimiting effects and/or changing system geometries must be considered. (Author)