Development of High Level Electrical Stress Failure Threshold and Prediction Model for Small Scale Junction Integrated Circuits.

摘要

This report summarizes the experimental and theoretical work performed in order to develop engineering type prediction techniques to predict both surge impedances and failure levels of small scale junction integrated circuits when exposed to EMP type environments. A further requirement was that these predictive techniques should not require a 'hands on' device evaluation but should relate the surge impedance and failure levels to some associated device parameter which could easily be obtained from a manufacturer's data sheet or other published information. The data required to develop the models was obtained by a literature search of numerous DOD and NASA agencies and contractors. In addition, 252 integrated circuits were experimentally evaluated to determine their specific pulse response and damage characteristics. These 252 devices consisted of 11 individual part types, 7 digital part types and 4 linear part types. All pulse damage experiments were performed using unipolarity, single square wave pulses of 10 nanosecond to 1 microsecond duration. Models were generated for the power failure threshold as a function of pulse width, the current failure threshold as a function of pulse width and the impedance as a function of current.