A Quantitative Evaluation of the Feasibility of, and Suitable Hardware Architectures for, an Adaptive, Parallel Finite-Element System

摘要

This paper describes an experimental implementation of a design for an adaptive, parallel finite-element system. The implementation was used to simulate the performance of this design on several microprocessor-based multiprocessor architectures. We conclude that it will be possible to build hardware/software finite-element systems which exploit data segmentation to achieve flexibility, modularity, and the ability to process very large problems. (Author)