State-of-the-Art Assessment of Testing and Testability of Custom LSI/VLSI Circuits. Volume III. Fault Model Analysis.

摘要

Physical failure in LSI/VSLI circuits is highly dependent on the fabrication technology being used and result in a very complex faulty behavior. To reduce numbers and types of faults that must be handled for test generating and fault simulation, logic fault models are used. The most popular fault model is the single stuck line (SSL) which can emulate many common physical faults. Non-standard faults like short circuits are more difficult to model-usually require modification to the original circuit to allow use of SSL software. This approach is also ideal for handling Complementary Metal oxide Semiconductors faults. (Author)