Design Study for a New Pattern Recognition Accelerator

摘要

The design of a programmable high-performance processor VLSI device is consideredfor a wide variety of image signal processing applications, including the potential for high-speed pattern recognition (e. g., text character recognition), image analysis, graphics rendering, speech recognition, and other computationally intensive algorithms. The approach is described in detail and its performance is analyzed in the context of two computationally demanding algorithms: linear filtering (e. g., two-dimensional discrete cosine transform), and neural network evaluation for character recognition. Subject to verification by simulation, the design described meets the benchmark objectives of the study.