Design of Energy Efficient Dual Spacer Delay Insensitive Ripple Carry Adder with better Slew Rate

摘要

The main goal of this paper is to provide the low power solutions for Very Large ScaleIntegration (VLSI). Design of low power and area efficient logic systems forms an integral part in thefield of VLSI design. The addition is the most fundamental part in the arithmetic operations. To performfast arithmetic operation, Ripple carry adder (RCA) is one of the fastest adder used in many dataprocessing applications. Various Delay Insensitive techniques are available for designing low powerapplications. In this paper, the features of Multi-threshold Null Convention Logic (MTNCL) arediscussed and we implement Ripple Carry Adder using proposed Multi-threshold Dual-Spacer Dual-RailDelay-Insensitive Logic (MTD3L). Proposed and existing techniques are compared in terms of variousperformance metrics like power, delay, energy and slew rate.