A new stray-insensitive switched-capacitor (SC) biquad with a reduced number of capacitors is proposed. It is first conceived in the continuous time domain and then obtained by replacing the resistances by their SC equivalents. For this biquad, two designs ins-domain, with as many equal-valued SCs as possible, are developed. One design allows independent variation of the pole-frequency, #x3c9;p=2#x3c0;fp, and band width and the other allowes independent variation of#x3c9;pand the pole-Q.It is shown that theses-domain designs approach the exact design inz-domain when the clock frequencyfc#x2a7e;10fp.Finally, the equal-valued SCs are replaced by a single time-shared capacitor. The resulting biquad exhibits the same performance as the original one without the time shared-capacitor. Moreover, it uses a greatly reduced number of capacitors and thus it would require significantly less silicon area when implemented on a MOS chip. Practical results taken on a simulated biquad with discrete components are in close agreement with the theoretical ones.
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