Robust Data Communication System Using Microprocessor-Based Sequential Decoder

摘要

A microprocessor-based sequential docoder employing Fano's algorithm for rate-half non-systematic convolutional code of constraint length three is discussed. The decoder is implemented on the VMC-85 microprocessor kit, which employs the Intel 8085A as its CPU. The encoder is realized through a hardware external to the microprocessor. Fixed and random errors are added to test the performance of the sequential decoder. Tests with fixed errors show that the decoder can correct any two errors in sixcode bits. Experimental performance of the decoder for data transmission in the presence of random errors has been evaluated and it is found that BER is improved from 10#x2212;3at the input to better than 10#x2212;6at the output. A coding gain of 0.8 dB at BER of 10#x2212;5has been achieved.