High Speed Carry Select Adder Using Prefix-Adders for ALU Application

摘要

High performance digital adder with low power consumption and reduced area is an important design constraint for advanced processors. For such an adder the speed of operation is restricted by carry propagation from input to output. In carry propagation design, carry select adder (CSLA) provides a good compromise between cost and performance. In this paper carry select adder using prefix adders i.e., by replacing Ripple Carry Adder (RCA) with Cin = 0 with Kogge Stone Adder (KSA) is implemented to reduce delay between intermediate stages with increase in area. At gate level, the KSA is modified to reduce the area of the design. To reduce area and power of the design, the other group of RCA i.e., RCA with Cin = 1 is also replaced with add-one circuit. The proposed architecture shows that there is a reduction of area, delay and power. Based on this architecture, we designed 4-, 8-, 16-, 32-and 64-bit square-root CSLA (SQRT CSLA) and compared with the respected conventional and modified SQRT CSLA. In this work, the proposed designs are developed using verilog-HDL and the performance is evaluated using 180-ηm CMOS technology in Cadence tools. The comparison results show that the proposed SQRT CSLA is faster compared to conventional SQRT CSLA and modified SQRT CSLA.